The following description is provided to assist the understanding of the reader. None of the information provided or references cited is admitted to be prior art.
A memory device stores content data and outputs the stored content data when requested. In one implementation, an external controller provides an external clock signal (e.g., read enable (RE) clock signal) to the memory device for data read operations. In return, the memory device outputs, to the controller, output data including the stored content data along with a DQS strobe signal generated based on the RE clock signal. The time after which a DQS strobe signal (also referred to herein as a “DQS strobe”) is generated once an edge (e.g., rising edge) of a valid RE clock signal (e.g., rising edge of RE Clock signal) is received is referred to as a data access time tDQSRE. The data access time within a data access time tDQSRE range (also referred to as “a data access time range” or “tDQSRE range” herein) enables a successful memory read operation.
In one approach, the data access time tDQSRE is calibrated by comparing the RE clock signal and the DQS strobe, and sequentially modifying the DQS strobe. For example, the DQS strobe may be modified to be synchronous to a modified RE clock signal generated by adding delay to the RE clock signal. The delay may be sequentially increased for multiple cycles of the RE clock signal until the data access time tDQSRE is within the data access time tDQSRE range. However, sequentially calibrating the DQS strobe for multiple RE clock cycles may take a while, and accordingly the data throughput may be decreased due to the extended calibration.